1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a metal oxide semiconductor electric field effect transistor (hereafter, called a MOSFET) forming a tunneling insulation between a channel region and one of a source region and a drain region.
2. Background of the Related Art
As shown in FIG. 1, a related art MOSFET includes a gate electrode 15 for applying a voltage for inducing an electric field effect in a semiconductor substrate 11, a gate oxide film 14 formed between the semiconductor substrate 11 and the gate electrode 15, a source region 12 for supplying a charge, a drain region 13 for drawing out a charge, and a channel region 11' formed between the source 12 and the drain 13.
As shown in FIG. 2A, in fabricating the MOSFET, a gate oxide film 14a and a polycrystalline polysilicon film 15a for forming a gate electrode are sequentially formed on the semiconductor substrate 11. Then, as shown in FIG. 2B, the gate electrode 15 is formed by patterning the polysilicon film 15a. As shown in FIG. 2C, a buffer oxide film 16 is formed on the entire resultant structure. Then, using the gate electrode 15 as a mask, an impurity is implanted into the semiconductor substrate 11 at both sides of the gate electrode 15 to respectively form the source region 12 and the drain region 13 and remove the buffer oxide film 16.
In the related art MOSFET fabricated according to the above-described method, an n-type impurity is implanted into a p-type semiconductor substrate to form the source and drain regions for an n-channel MOSFET. Similarly, a p-type impurity is implanted into an n-type semiconductor substrate to form the source and drain regions for a p-channel MOSFET.
When a fixed voltage is applied to the gate electrode 15, an n-type inversion layer 11' is induced in the semiconductor substrate 11. As a result, the source 12 and the drain 13 are electrically connected by the inversion layer 11'. Hereafter, the n-type inversion layer 11' electrically connecting the source 12 and the drain 13 is called an induced channel region 11'. When the channel region 11' is induced and a voltage is applied to the drain 13, electrons move freely the channel region 11' moves freely and consequently, a current flows between the source 12 and the drain 13.
With the increasing integration of semiconductor memory devices, the size of the MOSFET is accordingly being reduced and the length of the channel is shortened. Therefore, a threshold voltage Vth reduction problem becomes serious because of a short channel effect, and a leakage current flows between the source 12 and the drain 13 when no voltage is applied to the gate electrode 15. The leakage current degrades an operational characteristic of the transistor and generates a punchthrough phenomenon where the transistor cannot be controlled by a voltage applied to the gate electrode 15.